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About Programmable Logic

Word Origin and Invention Origin

Programmable logic first arose in 1970 with the Texas Instruments TMS2000, a chip programmed during production using a masking process. TI coined the term Programmable Logic Array during this period.

Then in 1971, General Electric Company developed an experimantal programmable logic device (PLD) based on new PROM technology. This General Electric device was the first PLD ever developed, predating the Altera EPLD by over a decade.

Like many other developments in electronics, the industry has driven the terminology of these emerging technologies. As usual, the reader should expect overlaps of terms and marketing jargon as we wade into these most interesting chips.

Many of these chips on the market are field-programmable, this is not the same as the term field-effect which refers to certain semiconductor technology; instead, field-programmable means that the chips can be programmed in the field. The earliest commercial PLDs, rather than in the field, were programmed during the manufacturing process.

Simple Explanation

First, lets look at a non-programmable logic device. A CPU (Central Processing Unit) in simplified terms is perhaps the most general purpose and powerful logic device on the market. Every personal computer has a CPU that underpins the entire system. The CPU can do math, handle memory addressing, and process commands of all kinds, and the CPU can do these things because it has a complex logic structure hard-wired inside.

Like a CPU, a PLD (Programmable Logic Device) has an internal logic structure; but unlike a CPU, the PLD's structure is configurable, programmable in much the same way that a PROM memory is programmable. These chips can be programmed to perform all manner of tasks, from very simple comparator operations to complex software-like functions … all in hardware!

A PLD is a combination of a logic device and a memory device. The memory is used to store the logic pattern that was given to the chip during programming. Most of the methods for storing data in an integrated circuit have been adapted for use in PLDs. These include:

  • Antifuses
  • SRAM
  • EPROM or EEPROM cells
  • Flash Memory

Programmable logic is similar enough in principle to memory that memory chips are sometimes used by hobbyists to make what is called a “poor man's PAL,” but a bonafide PLD can do far more.

All PLD programs can be designed using special programming languages that are then converted (“assembled”) into the logic patterns that will be configured on the chip. This significantly simplifies the design process.

Kinds and their Uses

SPLD: Simple Programmable Logic Devices are the most basic PLD, and depending on the size, can replace several 7400 series Transistor-Transistor-Logic (TTL) devices.

Kinds:

  • PAL (Programmable Array Logic): Typically contains no more than a few hundred programmable logic macrocells. Each macrocell is capable of performing a logic operation on its inputs. PALs are programmed using fuse and antifuse technologies, making the programming process irreversible.
  • PLA (Programmable Logic Array): Similar to PAL
  • GAL (Generic Array Logic): Same as PAL, but with one exception... it's erasable. These devices employ erasable memory technologies (EPROM, EEPROM, flash, etcetera) to store the logic configuration.
  • PEEL (Programmable Electrically Erasable Logic): Similar to GAL

Programming:

CPLD: Complex Programmable Logic Devices are the next step up from SPLDs, and often contain the equivalent of several SPLDs within one chip. A typical CPLD can contain thousands of macrocells, which are configured in blocks with programmable inter-connections.

Kinds:

  • PEEL (Programmable Electrically Erasable Logic): Similar to the GAL SPLD, but can come in these larger CPLD sizes as well.
  • EPLD (Erasable Programmable Logic Device)
  • EEPLD (Electrically Erasable Programmable Logic Device)
  • MAX (Multiple Array matriX)

Advantages:

  • The equivalent of many SPLDs in one chip
  • Supported by many of the same programming languages as SPLD's
  • High performance. Fast pin-to-pin throughput

Disadvantages:

  • Can have difficulty maintaining the same pin-out when reprogramming (depending on architecture)
    • Cheaper chips can have limited programmable block inter-connections

Programming:

  • Chip functionality is written in a specialized programming language and then converted to a logic pattern that will fit on the chip.
  • Many recent introductions to the market are In System Programmable (ISP), using flash based memory for their configurations.
    • Many ISP chips used to only be programmable via proprietary methods specific to each manufacturer, but many newer CPLDs conform to the JTAG ISP standard
  • Most CPLDs are reprogrammable using non-volatile EPROM, EEPROM, or flash memory technologies.
  • Many EPROM-based CPLDs are OTP (One Time Programmable), lacking a UV window.

Erasure:

  • Depends on the memory technology each chip is based on
  • EPROM-based chips are often OTP, lacking a UV window

General Notes: Chips do vary in architecture between manufacturer and model.

FPGA: Field Programmable Gate Arrays are the largest of the PLD family and have a different basic architecture (Look-up-tables) than the others (Sea-of-gates). FPGAs were originally called field programmable because they were designed to be programmed in the field. Many FPGAs today remain specifically field programmable … even to the point that they store their programming in volatile memory and have to be reloaded every time they power up.

Kinds:

  • Note: Many of these are manufacturer specific product lines. They can be based on all kinds of memory technologies, but primarily SDRAM and Antifuse.
  • LCA (Logic Cell Array)
  • pASIC (Programmable ASIC)
  • FLEX
  • APEX
  • ACT
  • ORCA
  • Virtex

Advantages:

  • Shorter time-to-market than ASICs (ASIC = application-specific integrated circuit)
  • Often reprogrammable in the field
  • Capable of more complex logic configurations than CPLDs

Disadvantages:

  • Can't handle designs that are as complex as those ASICs are capable of.
  • Consume more power than an ASIC
  • Volatile types have to be paired with non-volatile devices that can “boot” the FPGA and load its configuration at power-on.

Programming:

  • Chip functionality is written in a specialized programming language and then converted to a logic pattern that will fit on the chip
  • Many of these chips are SDRAM based, requiring that their programming be reloaded every time the chips are powered up.
    • Many FPGAs conform to the JTAG ISP standard and have a JTAG port for programming and debugging
  • Be aware that not all FPGAs are SDRAM based, some are non-volatile, and some are OTP (One Time Programmable).

Erasure:

  • Depends on the memory technology each chip is based on. SDRAM based chips are naturally erased every time the power is removed.

JTAG: This is not a kind of chip, but rather is a programming and interfacing standard common to many CPLDs and FPGAs. JTAG is the Joint Test Action Group of the IEEE (Institute of Electrical and Electronics Engineers), and over the years JTAG's name has become synonymous with its widely used standard for accessing sub-blocks of integrated circuits.

General Notes:

  • The JTAG interface is a special four or five pins, called the JTAG “port,” included on a chip. These ports can be daisy-chained together from one chip to another.
  • The PCI bus-connector-standard contains optional JTAG signals on pins 1-5
  • High-end embedded systems can have a JTAG port.
  • PCI-Express contains JTAG signals on pins 5-9

Uses:

  • Programming, testing, and debugging PLD chips and circuit boards
  • A special JTAG card can be used to reflash a corrupt BIOS
  • Almost all FPGAs and CPLDs used today can be programmed via the JTAG port.

Adapter Hardware:

  • There are no official standards for JTAG adapter physical connectors, but most manufacturers use standard 2.54mm pin header.
  • Most common JTAG pinouts are:
    • ARM 2x7 or 2x10 pin, used by almost all ARM based systems
    • MIPS EJTAG (2x7 pin) used for MIPS based systems
    • 2x5 pin Altera ByteBlaster-compatible JTAG used by many vendors (i.e. Atmel's AVR 8-bit and 32-bit processors)
    • 8pin (single row) generic PLD JTAG compatible with many Lattice ispDOWNLOAD cables

JTAG Software:

  • Open Source:
    • The UrJTAG project supports many JTAG tools, processors, and boards.
    • The OpenOCD project supports various inexpensive JTAG adapters including USB ones based on FT2232 chips, and is mostly used with ARM projects. It provides GDB and telnet interfaces, both from Linux and from MS-Windows.
  • Freeware:
    • (Because it is so important for developing modern embedded systems software, many chip vendors make a point of providing at least low-end JTAG software at no cost. )
    • Atmel provides [AVR Studio] on MS-Windows, for AVR8 microcontrollers, and a cross-platform AVR32studio product to support AVR32 systems.
    • Xilinx provides lower end FPGA development tools at no cost